1. Field of the Invention
The present invention generally relates to an amplifier circuit for amplifying an AC (alternating current) signal to derive signals having a plurality of desirable signal levels. More specifically, the present invention is directed to an amplifier circuit having a circuit arrangement suitable for an integrated circuit (IC).
2. Description of the Related Art
Referring now to FIG. 1, a conventional amplifier circuit will be described. This amplifier circuit is of a one-input/two-output amplifier circuit comprising a plurality of differential-input amplifiers, which amplifies one AC input signal containing a DC (direct current) voltage component so as to obtain a plurality of output signals therefrom.
In FIG. 1, the one-input/two-output amplifier circuit includes: a differential-input preamplifier 1 (simply referred to as a "preamplifier") having a non-inverting input terminal 1a; an inverting input terminal 1b; and an output terminal 1c; a first differential-input amplifier 2 (simply referred to as a "first amplifier") having a gain "kb" and connected to the output terminal 1c of the preamplifier 1. The first amplifier 2 includes a non-inverting input terminal 2a and an inverting input terminal 2b. The amplifier circuit further includes a second differential-input amplifier 3 (merely referred to as a "second amplifier") of a gain "kc" having a non-inverting input terminal 3a, and an inverting input terminal 3b; a signal input 4; a first output terminal 5 from which an output of the first amplifier 2 is derived, and a second output terminal 6 from which an output of the second amplifier 3 is derived.
The one-input/two-output amplifier circuit further includes: a resistor 7 having a resistance of "Ra.sub.1 " connected between the signal input 4 and the non-inverting input terminal 1a of the preamplifier 1; a resistor 8 having a resistance of "Ra.sub.2 " connected between the signal input 4 and the inverting input terminal 1b of the preamplifier 1; a capacitor 9 having a capacitance of "Ca" connected between the non-inverting input terminal "1b" of the preamplifier 1 and a ground; a resistor 10 having a resistance of "Rb.sub.1 " connected between the non-inverting input terminal "2a" of the first amplifier 2 and the output terminal 1c of the preamplifier 1; a resistor 11 having a resistance of "Rb.sub.2 " connected between the non-inverting input terminal "2b" of the first amplifier "2" and the output terminal 1c of the preamplifier 1; a capacitor 12 having a capacitance of "Cb" connected between the input terminal 2b of the first amplifier 2 and the ground; a resistor 13 having resistance "Rc.sub.1 " connected between the non-inverting input terminal 3a of the second amplifier 3 and the signal input 4; a resistor 14 having a resistance of "Rc.sub.2 " connected between the non-inverting input terminal 3b of the second amplifier 3 and the signal input 4; and a capacitor 15 having a capacitance of "Cc" connected between the inverting input terminal "3b" of the second amplifier 3 and the ground.
Operation of the above-described amplifier circuit as shown in FIG. 1 will now be described.
Upon receipt of an input signal containing a DC (direct current) voltage component supplied to the signal input 4, the input signal is supplied via the input resistors 7 and 8 to the non-inverting input terminal 1a and inverting input terminal 1b of the preamplifier 1, respectively. In this case, the signal input is directly supplied to the non-inverting input 1a of the preamplifier 1, whereas since an AC (alternating current) signal contained therein is bypassed via the capacitor 9 to the ground, only the DC voltage component contained therein is applied to the inverting input terminal 1b thereof. As a result, only the AC signal component of the signal input is supplied as the differential input of the preamplifier 1. This is because the lower cut-off frequency of the preamplifier 1 determined by the resistor 8 and capacitor 9 is selected to be sufficiently lower than that of the signal input.
In addition, the resistances of the input resistor 7 and 8 are equal to each other.
That is: EQU Ra.sub.1 =Ra.sub.2 = (1)
This is because generally speaking, the DC voltage difference which is produced by the DC bias current flowing through both the input terminals 1a and 1b of the differential-input preamplifier 1 and appears between the resistors, is set to be equal to each other, and then the DC balance of the differential input is to be precisely improved. It should be noted that if the characteristics of this DC voltage difference required for the preamplifier 1 (e.g., an asymmetrical distortion factor and an allowable range of DC operating-point variations for the amplifier stage succeeding to the signal input stage, and the like) are preset within a permissible range, the required resistance conditions are not limited to the above-described conditions. For instance, one input resistor 7 may be shortcircuited.
It should be understood that the above descriptions on the resistance conditions are similarly completely applicable to the remaining first and second amplifiers 2 and 3. Accordingly, in general, the resistance values of the respective input resistors are selected such that: EQU Rb.sub.1 =Rb.sub.2 =Rb (2) EQU Rc.sub.1 =Rc.sub.2 =Rc (3)
It should be noted that the following descriptions are based upon such an assumption that in order to simplify the contents of these descriptions, the input impedances of the respective amplifiers are selected to be sufficiently higher than those of the above-described resistors 10 to 14. This assumption is very commonly accepted as a method for designing an amplifier circuit and therefore is readily realized. One detailed amplifier-circuit designing method is as follows. As illustrated in FIG. 2, for instance, in the differential input amplifier circuit, if the DC current amplification factors (h.sub.FE) of the differential transistors TR1 and TR2 are set to be high, the DC bias currents I.sub.B1 -BIAS and I.sub.B2 -BIAS are preset to be low, or the common emitter resistor R.sub.E-COMMON of the differential transistors TR1 and TR2 is selected to be great, the desired amplifier-circuit design can be realized. Detailed information of this known designing method is described in, for instance, the book entitled "ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS" written by P. R. GRAY and R. G. MEYER, on pages 158 to 175, by JOHN WILEY & SONS, INC.
More practically, as illustrated in a circuit diagram of FIG. 3, an emitter follower circuit is added to the differential input terminals of the differential transistors TR1 and TR2, resulting in the high input impedance of the differential amplifier stage while maintaining freedom of the design of the differential amplifier stage. This practical solution is especially utilized for an integrated circuit. Moreover, as illustrated in FIG. 4, instead of the differential transistors TR1 and TR2, field-effect transistors FET1 and FET2 may be employed to satisfy the above-described conditions.
Referring back to the circuit diagram of FIG. 1, behavior of the respective signals will now be described.
Assuming that an input signal supplied to the signal input 4 is Vi(s), the differential input of the preamplifier 1 is Vai(s), the output of the preamplifier 1 is Vao(s), the differential input of the first amplifier 2 is Vbi(s), the output of the first amplifier 2 is Vbo(s). the differential input of the second amplifier 3 is Vci(s). and the output of the second amplifier 3 is Vco(s), the following equations are given: ##EQU1## where a symbol "s" represents a Laplace operator, or Laplacian.
Then, if the capacitances Ca, Cb and Cc of these capacitors 9, 12 and 15 are selected to be sufficiently great so as to sufficiently lower the following low cut-off frequencies "fa", "fb", and "fc" with respect to the frequency of the signal to be transmitted, i.e., ##EQU2## the respective output signals Vao, Vbo and Vco as represented by the above equations (5), (7) and (9) with respect to the signal to be transmitted are given: ##EQU3## Accordingly, these output signals are influenced by only the gains "ka" to "kc" of the respective amplifiers 1 to 3.
The DC signal behavior will now be considered with respect to the respective differential inputs of the amplifiers 1 to 3, s=0 in the above described equations (4), (6) and (8). EQU Vai(0)=0 (16) EQU Vbi(0)=0 (17) EQU Vci(0)=0 (18)
From these equations, the DC balance of the differential inputs of the respective amplifiers 1 to 3 can be maintained even if the DC voltage component contained in the signal input "Vi" varies.
As has been described above, the prior art amplifier circuit as illustrated in FIG. 1 can have the particular advantage that the differential-input DC balance can be maintained irrespective of the DC voltage component contained in the input signal. However, this amplifier circuit has a drawback that the capacitors 9, 12 and 15 for bypassing the AC signal are required for each of the amplifiers. As previously described, in order to sufficiently lower the low cut-off frequencies fa, fb, and fc with respect to the frequency of the signal to be transmitted, the capacitances of these capacitors (Ca, Cb, and Cc) must be selected to be large. Although there is another way that the resistances (Ra, Rb, Rc) of the respective input resistors are selected to be great, the following limitation to employ this solution may be provided. That is, if the resistances of the resistors become large, the high frequency characteristics are deteriorated at the non-inverting input due to the input capacitances of the respective amplifiers, and the noise characteristics of the amplifiers are deteriorated due to an increase of the resistor thermal noise.
When, for instance, the lower limit of the signal frequency to be transmitted is selected to be 100 Hz, the low cut-off frequencies fa, fb and fc must be sufficiently lower than this lower limit frequency.
If the low cut-off frequencies and the resistances of the input resistors are: EQU fa=fb=fc=10 Hz (19) EQU Ra=Rb=Rc=10 k.OMEGA. (20), and
then the capacitances of the AC signal bypassing capacitors 9, 12, and 15 are given by: EQU Ca=Cb=Cc=1.6 .mu.F (21)
Accordingly, when the amplifier circuit as illustrated in FIG. 1 is fabricated in an integrated circuit (IC) under the above-described circuit design, these AC signal bypassing capacitors must be externally connected to the IC module. Moreover, if IC pins for externally connecting these capacitors to the IC module must be required, then the number of pins must be equal to that of these capacitors. In addition, when the output circuits are increased in this amplifier circuit, the following drawbacks are provided.
FIG. 5 illustrates an amplifier circuit whose output circuit is increased by 1, as compared with that of the above-described amplifier circuit shown in FIG. 1. The amplifier circuit shown in FIG. 5 includes a third amplifier 16 having a gain of "kd", a non-inverting input terminal l6a, an inverting input terminal 16b, and a third output terminal 17 from which an output of the third amplifier 16 is derived; resistors 18 and 19, and an AC signal bypassing capacitor 20 having a capacitance of "Cd". It is of course that this amplifier circuit includes the same amplifying stages as in the first-mentioned conventional amplifier circuit.
It is apparent from this example that the more the number of the amplifier stages is increased, the more the number of the AC signal bypassing capacitors is increased. As a result, the IC pins for externally connecting the capacitors to the IC module must be increased.
As is well known in the art, not only a capacitance of an AC signal bypassing capacitor but also a resistance of a resistor cannot be designed to be extremely high in an IC module. In other words, the space for occupying such a capacitor or resistor cannot be designed to be great with respect to the entire region of the IC module, or chip. In general design concept, several ten pF (pico farads) for a capacitor and several ten k.OMEGA. (kilo-ohms) for a resistor are regarded as the practical limit values in view of space availability. As a consequence, it can be readily understood that the AC bypassing capacitor having the capacitance of 1.6 .mu.F as defined by the above equation (21) exceeds considerably over this limit value. Accordingly, this largecapacitance capacitor must be externally connected to the IC module, or chip by employing IC pins.
As previously described, since the AC signal bypassing capacitors of the conventional amplifier circuit must be employed, the number of which is equal to that of the amplifiers involved therein, the same number of the IC pins must be required for that of the AC signal bypassing capacitors when manufacturing the conventional amplifier circuit in an IC module, or chip. As a result, the size of the IC module is necessarily large, and then the large IC module must be manufactured at a higher cost.
It is therefore an object of the present invention t solve the above-described conventional drawbacks and thus provide an amplifier circuit in which the differential-input DC balance for a plurality of amplifiers involving a preamplifier (more than three amplifiers) can be effectively maintained by only a single AC-signal bypassing capacitor.